A method of the above mentioned general type is known from U.S. Pat. No. 5,504,033 (Bajor et al.), the disclosure of which is incorporated herein by reference for background.
In integrated circuits made of semiconductor material, active regions are separated and isolated from one another by so-called field regions. Examples of the active regions include individual transistors that are integrated into the same common substrate. The field regions are provided with insulating or isolating structures in order to avoid an undesired drift of charge carriers, i.e. electrons or holes, between the respective active regions. In integrated circuits based on silicon technology, it is known to isolate respective active regions on the surface of the circuit or device from each other by means of an isolating or insulating structure consisting of a silicon oxide (e.g. silicon dioxide), generally called a field oxide.
The insulation or isolation structure may, for example, be produced by means of the LOCOS (LOCal Oxidation of Silicon) technology, which involves the following process. First, the active regions of the circuit are covered by a structured or patterned silicon nitride layer. Next, the entire surface is oxidized. Since the conversion rate of silicon nitride into silicon dioxide amounts to only about 1% of the growth rate of the oxide on the uncovered (i.e. exposed) field regions of the integrated circuit, the isolation structure of silicon oxide grows preferentially in the field regions or field areas between the active regions of the integrated circuit.
A problem existing in the LOCOS technology relates to the formation of a so-called bird's beak structure characterized by a tapering or thinning of the oxide layer as well as an associated bird's head peak or ridge along the edge or perimeter of the nitride layer. This bird's beak structure arises as a result of a diffusion of oxidizing gases under the perimeter edge of the nitride layer. As a result, after the nitride layer is removed, there arises a gradual transition rather than a clean distinct boundary from the field oxide to the adjacent active region. The width and shape of the bird's beak structure determine the minimum spacing distance of neighboring active regions, and thus limit the achievable packing density of the active regions in the integrated circuit.
A further possibility for insulating or isolating active regions relative to one another is provided by the so-called STI (Shallow Trench Isolation) technology, whereby trenches are formed by an anisotropic etching process between active regions that have been covered with a nitride protective layer, and then the trenches are filled with an insulating material such as silicon dioxide or polysilicon. In this context, a trench is regarded as shallow in the sense of “Shallow Trench Isolation” if it has an aspect ratio, i.e. a ratio of trench depth to trench width, that is smaller than 1. Using STI technology, it is possible to achieve a higher packing density in comparison to the results of LOCOS technology.
In order to insulate or isolate active regions in the depth of the structure of the integrated circuit from one another, it is known to use so-called deep trenches and/or so-called wells or well regions for achieving the lateral isolation. A deep trench is characterized by an aspect ratio greater than 1, i.e. the trench is deeper than it is wide. A well is a three-dimensional region or portion of a semiconductor substrate, having majority charge carriers of a different conductivity type (for example P-type) in comparison to the majority charge carriers of the surrounding portion of the substrate around the well (for example N-type). As a result, blocking or non-conductive PN-junctions will be formed along the peripheral edges or boundaries of the wells, in connection with a suitable electrical reverse-biasing thereof, whereby these PN-junctions effectively electrically isolate the interior of the well from the surroundings thereof.
Such wells are typically produced through implantation of a dopant followed by thermally supported diffusion of the dopant into the semiconductor substrate. Since the diffusion is generally not directional, i.e. does not proceed along a preferred direction, the drive-in diffusion typically occurs both in the depth direction as well as in the width or lateral direction. Thus, the lateral spreading of the wells will become ever greater as the wells are diffused or driven deeper into the semiconductor substrate such as silicon, by a high temperature well drive step. In other words, as the dopant is diffused deeper into the substrate, it necessarily also spreads wider in the lateral direction. As a result, the mutual electrical influence or interference of adjacent wells on each other will also increase. Thus, the spacing distance between adjacent electrically active regions with different well dopings must be selected to be sufficiently large to prevent or avoid such an electrical influence between neighboring wells. A desired doping depth necessarily also always requires an associated certain width, which ultimately leads to undesired limitations of the packing density. Similar limitations arise in an analogous manner in connection with high dopant concentrations.